Embodiments of the inventive subject matter generally relate to the field of computers and, more particularly, to preemptive repair of memory for computers, apparatuses, devices, etc.
Modern computer systems typically are configured with a large amount of memory in order to provide data and instructions to one or more processors in the computer systems. Historically, processor speeds have increased more rapidly than memory access times to large portions of memory, in particular, DRAM memory (Dynamic Random Access Memory). Memory hierarchies have been constructed to reduce the performance mismatches between processors and memory. For example, most modern processors are constructed having an L1 (level 1) cache, constructed of SRAM (Static Random Access Memory) on a processor semiconductor chip. L1 cache is very fast, providing reads and writes in only one, or several cycles of the processor. However, L1 caches, while very fast, are also quite small, perhaps 64 KB (Kilobytes) to 256 KB. An L2 (Level 2) cache is often also implemented on the processor chip. L2 cache is typically also constructed using SRAM storage, although some processors utilize DRAM storage. The L2 cache is typically several times larger in number of bytes than the L1 cache, but is slower to read or write. Some modern processor chips also contain an L3 (Level 3) cache. L3 cache is capable of holding several times more data than the L2 cache. L3 cache is sometimes constructed with DRAM storage. L3 cache in some computer systems is implemented on a separate chip or chips from the processor, and is coupled to the processor with wiring on a printed wiring board (PWB) or a multi-chip module (MCM). Main memory of the computer system is typically large, often many GB (gigabytes) and is typically implemented in DRAM.
Main memory is typically coupled to a processor with a memory controller, which may be integrated on the same device as the processor or located separate from the processor, often on the same MCM (multi-chip module) or PWB. The memory controller receives load or read commands and store or write commands from the processor and services those commands, reading data from main memory or writing data to main memory. Typically, the memory controller has one or more queues, for example, read queues and write queues. The read queues and write queues buffer information including one or more of commands, controls, addresses and data; thereby enabling the processor to have multiple requests—including read and/or write requests, in process at a given time.
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved, innovative solutions for maximizing overall system performance and density by improving the memory system or memory subsystem design and structure. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, and the like. Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact, such as space, power and cooling.
As speeds of DRAM interfaces increase there becomes an increased probability of a read including a correctable error resulting from one or more of the memory devices, any interconnect structure in the memory signal path, the memory interface, coupled noise, power supply fluctuations or noise, temperature variations, timing drift, and the like.